A computer memory system typically includes a number of DRAM chips. The access time to these DRAM chips is relatively slow compared to the operating speed of the processor. In order to improve access time, a technique known as "interleaving" may be employed. Interleaving equally divides the DRAM chips into two large banks and stores data elements having successive addresses in alternate banks. By this method one bank can be accessed while the other is being precharged.
Some computer architectures permit multiple DRAM configurations both in the number and capacity of memory chips employed. Interleaving may be disrupted in configurations which allow the user to add more or larger capacity chips. For example, the size of the DRAM chips can change the absolute capacity of a memory bank or the relative size of two banks. Either of these can make a conventional interleaving architecture inoperative.
Non-interleaved systems will transfer data to memory relatively slowly. This can be particularly problematic with newer high performance architectures, such as microchannel, in which a "streaming mode" transfers data on every clock cycle. Memory controllers operating at the same speed as the microchannel are not able to handle streaming mode transfers without interleaving. Furthermore, some memory controllers are unable to handle data transfers on successive clock cycles irrespective of whether the controller is operating in interleaving mode.